This invention relates to a device for controlling data transfer between integrated circuit chips via a bus, and more particularly to a data transfer controlling device for improving the efficiency of data transfer between bus-coupled chips.
Personal computers and workstations have recently been provided with a display device which can simultaneously display multiple colors at a high resolution. Such a display device can provide representation of a structure of CAD and computer graphics in full color.
Such a display device generally has an all point addressable (APA) video buffer, and a function for rewriting the content of display by writing data as pixel values in this APA video buffer.
Typically, pixel operations for display include BITBLT (moving pixel values in a specific area to another area) as well as operations on a pixel basis (for example, changing color values).
In general, methods for assigning a color code to each pixel typically include the following two methods. The first method is to assign, for example, bits at coordinates (X, Y) on each plane of an image memory to corresponding pixels at coordinates (X, Y) of a screen over multiple planes of the image memory. According to this method, assuming that the data constituting one pixel consists of eight bits, with eight memory planes being prepared. Each plane is separately associated with a video processing unit (device) for processing bit data. That is, the first method is just arranged so that one pixel passes through eight planes (plane method).
Although the second method is similar to the first method in that a plurality of memory planes are prepared, each of which is separately coupled to a video processing unit, eight-bit data constituting one pixel resides on a memory plane directly coupled to the video processing unit (packed color method).
In accordance with the first method, the BITBLT can complete the operation in individual memory planes only, and does not require data transfer over different video chips through the bus, allowing high speed processing. However, if it is intended to perform processing for pixel values, independent processing is not sufficient any longer, and data processing becomes necessary so that the bit values are sent to a separate processing unit from each memory plane through the bus by operating the individual video chips. The bytes collected here are subject to predetermined processing, and the bit values are again allocated through the reversed path, thus significantly lowering the processing speed.
In accordance with the second method, because the color value of one pixel resides in the same memory plane, processing of the pixel value can be completed only in a single video chip, allowing high speed processing. However, to perform the BITBLT operation, it is necessary to transfer 8-bit pixel values between different video processing units. Usually, the data bus of a workstation has a width of as much as 64 bits. However, when it is intended by using such 64-bit width bus to transfer 8-bit data between chips, the data bit width for one cycle of data transfer is fixed for a conventional bus. Therefore, when data smaller than the bus width is intended to be transferred, the bus width cannot be effectively used.
In addition, there are known the following publications or prior art which relate to data transfer through a bus.
Published Unexamined Patent Application (PUPA) No. 63-27891 discloses a technique in which parameters such as a top write address or a page width are prepared in advance by software, and stored in a predetermined hold circuit, and that subsequent write addresses are automatically generated by hardware.
PUPA No. 1-14656 discloses a technique in which a transfer address is provided to the first memory and read to be temporarily held in a temporary hold register, and the data held in the temporary hold register is written in the second memory by providing a destination address to the second memory so that a large amount of data can be transferred at high speed.
PUPA No. 1-280796 discloses the arrangement of a plurality of extended registers so as to share an extended bit map memory, and to operate shift registers at different speeds.
PUPA No. 2-284253 discloses the provision of a control section between a high speed bus and a low speed bus which performs data transfer between a main memory and a plurality of I/0 memories. In the case of, for example, data transfer from the main memory of 32-bit width to an I/O memory of 16-bit width, this control section reads 4-byte data from the source address of the main memory, takes it once into a data register in a data transfer device, and releases the bus.
PUPA No. 3-204756 discloses the provision of an inter-bus data transfer device having a data register and an address register.
PUPA No. 3-259340 discloses the enabling of it to transfer a large amount of data at high speed by simultaneously taking in a plurality of instructions, by reading and temporarily storing them in a temporary hold register, and by providing a destination address to a second memory to write the data temporarily stored in the temporary hold register in the second memory.
PUPA No. 4-252386 discloses the increasing of the speed of transferring data between devices by constituting with bus lines in a number larger than those of bits constituting one pixel without increasing the clock rate, and by transferring data of one or more pixels in one clock.
PUPA No. 4-265038 discloses making memory length variable in integer multiplication when the bit length of input data varies by providing a write address counter which carries a write clock in synchronization with the input data every time each internal memory counts the number of bits to be stored, and just counts the number of memories to generate write addresses and write control signals.
However, the technique recited in any of the above prior art has a problem in that data cannot be efficiently transferred on a bus with a predetermined bit width by a variable bus protocol.